1. Field of the Invention
The present invention generally relates to a method of providing identification marks on a surface of a semiconductor package and more particularly to a wafer level chip scale package and a method of laser marking the same.
2. Description of the Related Art
Product information (such as part number, pin 1 location and identifying logo) is conventionally provided by means of a mark on the unbumped surface of a chip scale package (CSP). For CSPs manufactured using wafer level packaging technology, such marks are typically formed by either ink or laser marking the back surface of the wafer.
An example of ink marking is disclosed in U.S. Patent Application Publication No. 2004/0188860. A chip scale package includes an ink mark printed and cured on the backside surface of the CSP. While this method is “non-destructive” in the sense that no damage is done to the backside surface, ink marks are not durable and may be damaged in subsequent handling of the CSP, particularly if the ink mark is printed on a smooth surface.
Laser marking provides a durable mark and the identification mark may be formed directly on the silicon of the backside surface or indirectly on a layer formed or applied over the silicon of the backside surface. Examples of direct marks are disclosed in U.S. Pat. Nos. 6,248,973, 6,261,919 , 6,374,834, and 6,596,965. Examples of indirect marks are disclosed in U.S. Pat. Nos. 5,610,104, 6,023,094, 6,683,637, and 7,238,543.
Known laser marking techniques are not well suited for wafer-level CSPs having a back metal such as power MOSFETs, and more particularly, common drain MOSFETs used in battery protection applications. Direct marking of such MOSFET backside surfaces cuts through the back metal, adversely affecting lateral current flow through the back metal and increasing the resistance thereof.
Indirect marking on a coating or film applied to the MOSFET backside surface does not have these adverse effects upon the electrical performance of the chip. However, the resulting sandwich structure (Si/metal/organic film) of the backside surface leads to micro-chipping during dicing of the wafer due to the different mechanical properties of the components of the sandwich structure. Additionally, applying the coating or film adds to the cost of the wafer level CSP manufacturing process. Other approaches require special equipment, or require thick wafers for convenient handling and are not suitable for thin wafers.
In view of the limitations of the prior art, there is a need in the art for a method of laser marking a wafer level CSP having a back metal.